In many digital communication systems, data is transmitted as a sequence of high and low voltage signals without an accompanying clock signal. In addition, many systems support multiple sampling rates of the signal. For an unknown digital signal, a receiver can therefore need to determine the incoming sampling rate. Rate determination of and synchronization to a received signal are often difficult to accomplish for a conventional digital signal, particularly if there are long stretches of high digital values or low digital values. During such periods, there are no transitions in the signal that can be used as a reference for synchronization or rate synchronization.
Biphase mark coding (BMC) was developed to address this difficulty in traditional digital signals. Like a traditional digital signal, one bit is transmitted for each clock cycle. Unlike a traditional digital signal, between each bit a transition in polarity (from high to low or low to high) occurs. In order to transmit a “1” value, a transition also occurs after half a clock cycle (a clock cycle can also be referred to as a cell). To transmit a “0” value, no transition occurs in the middle of a cell. Therefore, to decode a signal encoded using BMC, a determination in each cell is made as to whether a transition occurs in the middle of the cell or not. If no transition occurs, a “0” value is interpreted, and if a transition occurs a “1” value is interpreted.
FIG. 1 illustrates a signal encoded using BMC. Signal 102 is a reference clock signal, signal 104 is a source digital data signal and signal 108 is a BMC encoded digital signal. The binary values are indicated by arrow 106. The BMC encoded signal has an equal number of highs and lows.
Preambles can also be added to a BMC-encoded signal. The preamble is defined by communications protocol used and can comprise one or more intervals of 1½ cell periods with no transitions. When using BMC, a transition should occur at least within 1 cell period, so an interval of 1½ cell periods cannot occur normally as part of the incoming data. The preamble thus provides an anomaly which can be located for synchronization purposes.
FIG. 2 illustrates preambles used in the Sony/Phillips Digital Interconnect Format (SPDIF). The B preamble 202 comprises 4 cells, but contains two intervals of 1½ cell periods with no transition (indicated by arrows 212 and 214), and is an instance of a preamble when the preceding cell concluded with a low value. B preamble 204 is an instance of a preamble with a complementary polarity that is used when the preceding cell concludes with a high value. The SPDIF format also defines an “M” preamble and a “W” preamble. M preambles are indicated by arrow 222 and by arrow 224, having complementary polarity. W preambles are indicated by arrow 232 and by arrow 234, having complementary polarity.
The preambles enable receivers to more easily synchronize an incoming data signal to an internal clock signal and to recover the data, such as by using a phase locked loop (PLL) to phase align a transition in the incoming data signal to a clock signal.